1. Field of the Invention
This invention relates to integrated circuit structures, and in particular to a process for fabricating insulating regions of oxidized semiconductor material in such structures in which the insulating regions do not encroach into the surrounding semiconductor material and which insulating regions have an upper surface planar with respect to the semiconductor substrate.
2. Description of the Prior Art
In the fabrication of integrated circuits, large numbers of active and/or passive electronic components are formed in a single substrate of semiconductor material, typically monocrystalline silicon. For the proper functioning of individual components or groups of components, these components or groups must be electrically isolated from each other. This electrical isolation prevents currents or voltages which are induced in one part of the circuit from being communicated to another part of the circuit where they are not desired.
Numerous techniques are known for providing such electrical isolation in an integrated circuit structure. Among known techniques are pn junctions (U.S. Pat. No. 3,117,260 to Noyce), dielectric isolation (U.S. Pat. No. 3,391,023 to Frescura), mesa etching (U.S. Pat. No. 3,489,961 to Frescura), and oxide isolation (U.S. Pat. 3,648,125 to Peltzer). Oxide isolation refers to the technique by which selected regions of semiconductor material in the integrated circuit are oxidized and thereby converted from being semiconducting material to electrically insulating material.
One known technique for fabricating oxide isolation regions in semiconductor structures is disclosed in U.S. Pat. No. 3,648,125 issued to Douglas Peltzer and entitled: "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure." The Peltzer patent teaches formation of oxidized regions of semiconductor material, typically silicon dioxide, by etching annular grooves in the surface of the integrated circuit which will surround subsequently formed components. These grooves are then oxidized to create regions of oxidized semiconductor material which extend vertically into the integrated circuit structure to contact a laterally extending pn junction. Thus all electronic components above the pn junction and within the annular ring of oxidized semiconductor material will be electrically isolated from surrounding components. Because the pn junction is usually created by epitaxially depositing silicon over a substrate, the region of silicon above the isolating pn junction and surrounded by the oxidized material is termed an "epitaxial pocket."
Unfortunately, most conventional techniques of fabricating oxide isolation, although widely used in the semiconductor industry, suffer from a disadvantage known as the "bird's beak" or "encroachment." For example, U.S. Pat. No. 4,168,999 teaches one technique for minimizing, but not eliminating, encroachment. Encroachment is illustrated in FIGS. 1 and 2 herein and is discussed below. Briefly, because oxidization of semiconductor material is an isotropic process, regions of oxidized semiconductor material formed in depressions in an otherwise flat surface will slope into the adjoining regions of semiconductor material. This phenomenon is known as encroachment or the "bird's beak" effect. Encroachment is undesirable because it uses additional amounts of the surface of the integrated circuit structure. Further, because of the encroachment of the insulating regions into the non-insulating regions, a parasitic region of semiconductor material is created beneath the "bird's beak." This parasitic region stores electrical charge when underlying layers are electrically biased. The parasitic region slows the operation of electronic components fabricated within the epitaxial silicon pocket. Additionally, oxidized semiconductor material formed using conventional techniques protrudes upwards from the surface of the surrounding material. This upward projection of the oxide isolation regions makes subsequent formation of conducting or insulating layers across the surface of the integrated circuit structure difficult. Such subsequently formed layers have a propensity to crack where they cross the upward projections.
One technique for eliminating encroachment in an oxide isolated integrated circuit structure is mentioned in U.S. Pat. No. 4,111,720 entitled "Method of Forming a Non-Epitaxial Bipolar Integrated Circuit," and issued to Michel et al. That patent discloses that recessed regions of silicon dioxide may be formed by sputter etching the substrate then depositing silicon dioxide. Unfortunately, this technique also suffers from a disadvantage in that it is difficult to create a planar upper surface when depositing silicon dioxide. The disadvantages of non-planar surfaces are well-known and include the difficulty of forming electrical connections traversing the surface.